Epson Research and Development
Vancouver Design Center
FPFRAME
(DY)
GPIO1
(YSCL)
GPIO0
(XINH)
FPDAT[17:0]
(R,G,B)
GPIO2 (FR)
(odd frame)
GPIO2 (FR)
(even frame)
Symbol
FPFRAME pulse width
t1
Horizontal total period
t2
t3
Vertical display start
1. Ts
= pixel clock period
Hardware Functional Specification
Issue Date: 01/11/13
t1
t3
Figure 6-39: 320x240 Epson D-TFD Panel Vertical Timing
Table 6-33: 320x240 Epson D-TFD Panel Vertical Timing
Parameter
Vertical Total = 250HT
line2
line1
t2
Min
Typ
Max
200
400
400
Page 89
Units
Ts (note 1)
Ts
Ts
S1D13706
X31B-A-001-08