Table 6-22: Single Color 16-Bit Panel A.c. Timing; Figure 6-26: Single Color 16-Bit Panel A.c. Timing - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center
Sync Timing
FPFRAME
DRDY (MOD)
Data Timing
FPSHIFT
FPDAT[15:0]
Symbol
t1 FPFRAME setup to FPLINE falling edge
t2 FPFRAME hold from FPLINE falling edge
t3 FPLINE period
t4 FPLINE pulse width
t5 MOD transition to FPLINE rising edge
t6 FPSHIFT falling edge to FPLINE rising edge
t7 FPSHIFT falling edge to FPLINE falling edge
t8 FPLINE falling edge to FPSHIFT falling edge
t9 FPSHIFT period
t10 FPSHIFT pulse width low
t11 FPSHIFT pulse width high
t12 FPDAT[15:0] setup to FPSHIFT rising edge
t13 FPDAT[15:0] hold to FPSHIFT rising edge
t14 FPLINE falling edge to FPSHIFT rising edge
1. Ts = pixel clock period
2. t1 = HPS + t4
min min
3. t2 = t3 - (HPS + t4
min min
4. t3 = HT
min
5. t4 = HPW
min
6. t5 = HPS - 1
min
7. t6 = HPS - (HDP + HDPS) + 2, if negative add t3
min
8. t14 = HDPS - (HPS + t4
min
Hardware Functional Specification
Issue Date: 01/11/13
FPLINE
FPLINE

Figure 6-26: Single Color 16-Bit Panel A.C. Timing

Table 6-22: Single Color 16-Bit Panel A.C. Timing

Parameter
)
min
), if negative add t3
min
t1
t4
t5
t6
t8
t7 t14
t12
min
min
t2
t3
t9
t11 t10
t13
1 2
Min Typ Max
note 2
note 3
note 4
note 5
note 6
note 7
t6 + t4
t14 + 3
5
2
2
2
2
note 8
Page 71
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
S1D13706
X31B-A-001-08