Table 6-9: Motorola Mc68K #1 Interface Timing - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center
Symbol
f Bus Clock Frequency
CLK
T Bus Clock period
CLK
t1 Clock pulse width high
t2 Clock pulse width low
A[16:1], M/R# setup to first CLK rising edge where CS# = 0,
t3
AS# = 0, UDS# = 0, and LDS# = 0
t4 A[16:1], M/R# hold from AS# rising edge
t5 CS# setup to CLK rising edge while CS#, AS#, UDS#/LDS# = 0
t6 CS# hold from AS# rising edge
t7a AS# asserted for MCLK = BCLK
AS# asserted for MCLK = BCLK ÷ 2
t7b
AS# asserted for MCLK = BCLK ÷ 3
t7c
AS# asserted for MCLK = BCLK ÷ 4
t7d
t8 AS# setup to CLK rising edge while CS#, AS#, UDS#/LDS# = 0
t9 AS# setup to CLK rising edge
UDS#/LDS# setup to CLK rising edge while CS#, AS#,
t10
UDS#/LDS# = 0
t11 UDS#/LDS# high setup to CLK rising edge
t12 First CLK rising edge where AS# = 1 to DTACK# high impedance
R/W# setup to CLK rising edge before all CS#, AS#, UDS# and/or
t13
LDS# = 0
t14 R/W# hold from AS# rising edge
t15 AS# = 0 and CS# = 0 to DTACK# driven high
t16 AS# rising edge to DTACK# rising edge
D[15:0] valid to third CLK rising edge where CS# = 0, AS# = 0 and
t17
either UDS# = 0 or LDS# = 0 (write cycle) (see note 1)
t18 D[15:0] hold from DTACK# falling edge (write cycle)
t19 UDS# = 0 and/or LDS# = 0 to D[15:0] driven (read cycle)
t20 DTACK# falling edge to D[15:0] valid (read cycle)
t21 UDS#, LDS# rising edge to D[15:0] high impedance (read cycle)
1. t17 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Hardware Functional Specification
Issue Date: 01/11/13

Table 6-9: Motorola MC68K #1 Interface Timing

Parameter
2.0V 3.3V
Min Max Min
20
1/f 1/f
CLK CLK
22.5 9
22.5 9
1 1
0 0
0 1
0 0
8
11
13
18
1 1
1 2
3 1
3 2
5 40 3
0 1
0 0
4 23 3
6 39 4
1 0
0 0
4 27 3
0
5 33 3
Page 45
Unit
Max
50 MHz
ns
ns
ns
ns
ns
ns
ns
8 T
CLK
11 T
CLK
13 T
CLK
18 T
CLK
ns
ns
ns
ns
14 ns
ns
ns
13 ns
16 ns
ns
ns
13 ns
2 ns
13 ns
S1D13706
X31B-A-001-08