S1D13706 Host Bus Interface; Host Bus Interface Pin Mapping - Epson S1D13706 Technical Manual

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3 S1D13706 Host Bus Interface

X31B-G-005-02

The S1D13706 directly supports multiple processors. The S1D13706 implements a 16-bit

Generic #2 Host Bus Interface which is most suitable for direct connection to the PC Card

bus. Generic #2 supports an external Chip Select, shared Read/Write Enable for high byte,

and individual Read/Write Enable for low byte.

The Generic #2 Host Bus Interface is selected by the S1D13706 on the rising edge of

RESET#. After RESET# is released, the bus interface signals assume their selected config-

uration. For details on the S1D13706 configuration, see Section 4.2, "S1D13706 Hardware

Configuration" on page 13.

The following table shows the functions of each Host Bus Interface signal.

Table 3-1: Host Bus Interface Pin Mapping

Although a clock is not directly supplied by the PC Card interface, one is required by the

S1D13706 Generic #2 Host Bus Interface. For an example of how this can be accom-

plished see the discussion on CLKI in Section 3.2, "Host Bus Interface Signals" on page

PC Card (PCMCIA)

External Decode

connect to HIO V

Inverted RESET

Epson Research and Development

Vancouver Design Center

Interfacing to the PC Card Bus

Issue Date: 01/02/23

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