Figure 6-28: 18-Bit Tft Panel Timing - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center
6.4.9 9/12/18-Bit TFT Panel Timing
FPFRAME
FPLINE
FPDAT[17:0]
DRDY
FPLINE
FPSHIFT
DRDY
FPDAT[17:0]
Note: DRDY is used to indicate the first pixel
Example Timing for 18-bit 320x240 panel
VDP = Vertical Display Period
= VDP Lines
VNDP = Vertical Non-Display Period
= VNDP1 + VNDP2
= VT - VDP Lines
VNDP1 = Vertical Non-Display Period 1
= VNDP - VNDP2 Lines
VNDP2 = Vertical Non-Display Period 2
= VDPS - VPS Lines
HDP = Horizontal Display Period
= HDP Ts
HNDP = Horizontal Non-Display Period
= HNDP1 + HNDP2
= HT - HDP Ts
HNDP1 = Horizontal Non-Display Period 1
= HDPS - HPS Ts
HNDP2 = Horizontal Non-Display Period 2
= HPS - (HDP + HDPS) Ts
Hardware Functional Specification
Issue Date: 01/11/13
LINE240
HNDP
1
invalid

Figure 6-28: 18-Bit TFT Panel Timing

VNDP VDP
2
LINE1
HDP
1-1 1-2
if negative add VT
if negative add HT
if negative add HT
VNDP
1
LINE480
HNDP
2
1-320
invalid
X31B-A-001-08
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S1D13706