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Horizontal Display Period Start Position Register 0
REG[16h]
7
6
Horizontal Display Period Start Position Register 1
REG[17h]
7
6
bits 9-0
S1D13706
X31B-A-001-08
Horizontal Display Period Start Position Bits 7-0
5
n/a
5
Horizontal Display Period Start Position Bits [9:0]
These bits specify a value used in the calculation of the Horizontal Display Period Start
Position (in 1 pixel resolution) for TFT, HR-TFT and D-TFD panels.
For passive LCD panels these bits must be set to 00h which will result in HDPS = 22.
HDPS = (REG[17h] bits 1-0, REG[16h] bits 7-0) + 22
For TFT/HR-TFT/D-TFD panels, HDPS is calculated using the following formula.
HDPS = (REG[17h] bits 1-0, REG[16h] bits 7-0) + 5
For further information on calculating the HDPS, see the specific panel AC Timing in Sec-
tion 6.4, "Display Interface" on page 56.
Note
This register must be programmed such that the following formula is valid.
HDPS + HDP < HT
4
3
4
3
Epson Research and Development
Vancouver Design Center
Read/Write
2
1
Read/Write
Horizontal Display Period
Start Position Bits 9-8
2
1
Hardware Functional Specification
Issue Date: 01/11/13
0
0
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