Epson S1D13706 Technical Manual page 276

Page 16
S1D13706
X31B-B-001-03
Frame Rate
Pixel Clock
TFT/FPLINE (pixels)
Select the desired frame rate (in Hz) from the drop-
down list. The values in the list are the range of possible
frame rates using the currently selected pixel clock. To
change the range of frame rates, select a different Pixel
Clock rate (in MHz).
Panel dimensions are fixed therefore frame rate can
only be adjusted by changing either PCLK or non-
display period values. Higher frame rates correspond to
smaller horizontal and vertical non-display values, or
higher frequencies.
Select the desired Pixel Clock (in MHz) from the drop-
down list. The range of frequencies displayed is
dependent on settings selected on the Clocks tab.
For example:
If CLKI is chosen to be Auto and PCLK is sourced from
CLKI on the Clocks tab, then the range for Pixel Clock
will range from 1.5 MHz to 80 MHz.
Selecting a fixed PCLK on the Clocks tab, say 25.175
MHz, will result in only four selections: 6.293, 8.392,
12.587, and 25.175 MHz. (these frequencies represent
the four possible frequencies from a fixed 25.175 MHz
input clock divided by the PCLK divider).
These settings allow fine tuning of the TFT line pulse
parameters and are only available when the selected
panel type is TFT/D-TFD/HR-TFT. Refer to S1D13706
Hardware Functional Specification, document number
X31B-A-001-xx for a complete description of the
FPLINE pulse settings.
Start pos - Specifies the delay (in pixels) from the start
of the horizontal non-display period to the leading edge
of the FPLINE pulse.
Pulse Width - Specifies the delay (in pixels) from the
start of the horizontal non-display period to the leading
edge of the FPLINE pulse.
Epson Research and Development
Vancouver Design Center
13706CFG Configuration Program
Issue Date: 01/03/29