Epson S1D13706 Technical Manual page 517

Epson Research and Development
Vancouver Design Center
Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4-2: CLKI to BCLK Divide Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4-1: Summary of Power-On/Reset Configuration Options . . . . . . . . . . . . . . . . . . . 14
Figure 2-1: MCF5307 Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2-2: MCF5307 Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2-3: Chip Select Module Outputs Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4-1: Typical Implementation of MCF5307 to S1D13706 Interface . . . . . . . . . . . . . . 13
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 01/02/23
List of Tables
List of Figures
Page 5
S1D13706
X31B-G-010-02