Interfacing To The Nec Vr4181A; The Nec Vr4181A System Bus; Overview - Epson S1D13706 Technical Manual

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2 Interfacing to the NEC VR4181A

X31B-G-008-02

The VR-Series family of microprocessors features a high-speed synchronous system bus

typical of modern microprocessors. Designed with external LCD controller support and

Windows® CE based embedded consumer applications in mind, the VR4181A offers a

highly integrated solution for portable systems. This section is an overview of the operation

of the CPU bus to establish interface requirements.

The NEC VR4181A is designed around the RISC architecture developed by MIPS. This

microprocessor is designed around the 100MHz VR4110 CPU core which supports the

MIPS III and MIPS16 instruction sets. The CPU communicates with external devices via

an ISA interface.

While the VR4181A has an embedded LCD controller, this internal controller can be

disabled to provide direct support for an external LCD controller through its external ISA

bus. A 64 to 512K byte block of memory is assigned to the external LCD controller with a

dedicated chip select signal (LCDCS#). Word or byte accesses are controlled by the system

high byte signal (#UBE).

Epson Research and Development

Vancouver Design Center

Interfacing to the NEC VR4181A™ Microprocessor

Issue Date: 01/02/23

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