S1D13706 Host Bus Interface; Host Bus Interface Pin Mapping - Epson S1D13706 Technical Manual

Embedded memory lcd controller

Hide thumbs Also See for S1D13706:

Table of Contents

3 S1D13706 Host Bus Interface

X31B-G-008-02

The S1D13706 directly supports multiple processors. The S1D13706 implements a 16-bit

Generic #2 Host Bus Interface which is most suitable for direct connection to the NEC

VR4181A microprocessor. Generic #2 supports an external Chip Select, shared Read/Write

Enable for high byte, and individual Read/Write Enable for low byte.

The Generic #2 Host Bus Interface is selected by the S1D13706 on the rising edge of

RESET#. After RESET# is released, the bus interface signals assume their selected config-

uration. For details on the S1D13706 configuration, see Section 4.2, "S1D13706 Hardware

Configuration" on page 13.

The following table shows the functions of each Host Bus Interface signal.

Table 3-1: Host Bus Interface Pin Mapping

Connect to HIO V

Interfacing to the NEC VR4181A™ Microprocessor

Epson Research and Development

Vancouver Design Center

Issue Date: 01/02/23

Table of Contents