Mc68030 To S1D13706 Interface; Hardware Description - Epson S1D13706 Technical Manual

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4 MC68030 to S1D13706 Interface

When connecting the S1D13706 RESET# pin, the system designer should be aware of all

conditions that may reset the S1D13706 (e.g. CPU reset can be asserted during wake-up

from power-down modes, or during debug states).

Figure 4-1: Typical Implementation of MC68030 to S1D13706 Interface

X31B-G-013-02

The interface between the S1D13706 and the MC68030 requires external glue logic.

Address decoding logic is required to provide the chip select (CS#) and memory/register

(M/R#) signals to the S1D13706 since the MC68030 does not have a chip select module.

SIZ1 is modified to signal the S1D13706 that 24-bit and 32-bit accesses are to converted

into word-byte and word-word accesses, respectively. Misaligned operands for 24-bit and

32-bit cycles are not supported with this external circuitry for SIZ1.RD# must be connected

to the following logic circuitry instead of directly to SIZ1.

RD# = '(SIZ0 & SIZ1').

The polarity of the WAIT# signal must be selected as active high by connecting CNF5 to

(see Table 4-1:, "Summary of Power-On/Reset Configuration Options," on

The diagram below shows a typical implementation of the MC68030 to S1D13706

The interface was designed using a Motorola MC68030 Integrated Development

Platform (IDP).

Decode Logic

System RESET

Interfacing to the Motorola MC68030 Microprocessor

Epson Research and Development

Vancouver Design Center

Issue Date: 01/02/23

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