Interrupt Status Register-3; I2C Mux Reset Register - Motorola IXP-9120 Reference Manual

Table 32: Interrupt Status Register-2
Bit
3
2
1
0

Interrupt Status Register-3

Address: C700 000E
Type: Read Only
This register provides Interrupt status. When interrupted, the NPU can interrogate the three
Interrupt status registers to determine the interrupt-source.
Table 33: Interrupt Status Register-3
Bit
3
2
1
0

I2C MUX Reset Register

Address: C700 000F
Type: Write Only
This register provides a means of resetting the 4-channel I2C switch, PCA9546. An active-
LOW reset input allows the PCA9546 to recover from a situation where one of the down-
stream I2C buses is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C state
machine and causes all the channels to be deselected, as does the internal power-on reset func-
tion.
Table 34:
Bit
0
Description
RFU
RFU
RFU
RFU
Description
0: Ejector handles are open
1: Ejector handles are closed.
0: Voltage Monitor Interrupt is active
1: Voltage Monitor Interrupt is inactive
0: Watchdog Timer Interrupt is active
1: Watchdog Timer Interrupt is inactive
RFU
I2C MUX Reset Register
Description
In order to reset the I2C MUX, this must be zero.
Reset value: 1
Access
Access
RO
RO
RO
Access
WO