Interface Signals; Disable Other Devices On The Spi Bus To Avoid Contention - Xilinx MIcroBlaze Development Spartan-3E 1600E Kit User Manual

Chapter 9: Digital to Analog Converter (DAC)

Interface Signals

Table 9-1
SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The
DAC_CS signal is the active-Low slave select input to the DAC. The DAC_CLR signal is
the active-Low, asynchronous reset input to the DAC.
Table 9-1: DAC Interface Signals
The serial data output from the DAC is primarily used to cascade multiple DACs. This
signal can be ignored in most applications although it does demonstrate full-duplex
communication over the SPI bus.

Disable Other Devices on the SPI Bus to Avoid Contention

The SPI bus signals are shared by other devices on the board. It is vital that other devices
are disabled when the FPGA communicates with the DAC to avoid bus contention.
Table 9-2
70
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3.3V
2.5V
Spartan-3E FPGA
SPI_MOSI
(N10) (T4)
DAC_CS
(N8)
SPI_SCK
(U16)
DAC_CLR
(P8)
SPI_MISO
Figure 9-2: Digital-to-Analog Connection Schematics
lists the interface signals between the FPGA and the DAC. The SPI_MOSI,
Signal FPGA Pin
SPI_MOSI T4
DAC_CS N8
SPI_SCK U16
DAC_CLR P8
SPI_MISO N10
provides the signals and logic values required to disable the other devices.
LTC 2624 DAC
REF A
DAC A
12
REF B
DAC B
12
REF C
DAC C
12
REF D
DAC D
12
SDI
CS/LD
SCK
SPI Control Interface
CLR
Direction
FPGA DAC Serial data: Master Output, Slave Input
FPGA DAC Active-Low chip-select. Digital-to-analog
conversion starts when signal returns High.
FPGA DAC Clock
FPGA DAC Asynchronous, active-Low reset input
FPGA DAC Serial data: Master Input, Slave Output
MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
Header J5
VOUTA
A
VOUTB
B
VOUTC
C
VOUTD
D
GND
SDO
VCC
(3.3V)
UG257_09_02_060606
Description
UG257 (v1.1) December 5, 2007
R