Sdi Transmitter - Xilinx VIODC User Manual

Chapter 6: SDI Interface
Table 6-5:

SDI Transmitter

Figure 6-3
provides either 74.25 MHz or 74.1758 MHz in HD mode or 54 MHz in SD mode. This
reference clock is connected directly to the REFCLK input of the RocketIO transceiver and
also buffered by a global clock buffer and distributed as the transmitter clock to all portions
of the transmitter section.
ICS664-02
BUFG
freq control
Pattern
Generator
DIP
switches
from
ML402
Pattern
Generator
The HD pattern generator produces four different video patterns for each of the eight HD
video formats supported. The video pattern and format is selected either by the DIP
switches on the VIODC or by the ML402 board. The HD pattern generator also produces
an 11-bit line number value. The line number is inserted into the video stream after each
End of Active Video (EAV) by the line number insertion logic. The Cyclic Redundancy
Check (CRC) block generates CRCs for both the Y and C channels and inserts them into the
video stream after the line number. Finally, the video is encoded for transmission by the
HD-SDI scrambler and provided to the RocketIO transceiver where it is serialized and sent
as an HD-SDI bitstream.
In SD mode, the clock from the ICS664-02 runs at 54 MHz. This is supplied to the RocketIO
transceiver where it is multiplied by 20, so that the actual data rate of the transceiver's
output is 1.08 Gb/s or 4X the 270 Mb/s SD-SDI bit rate. The SD pattern generator and the
other elements of the SD-SDI transmitter data path need to run at 27 MHz, so a clock
enable, asserted every other clock cycle, is generated and distributed to all elements of the
SD-SDI transmitter data path.
The SD pattern generator produces either National Television System Committee (NTSC) or
Phase Alternating Line ( PAL) component 4:2:2 video. The EDH processor calculates the
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48
ADV7321B Register Settings for PAL (Continued)
Register
Address
Name
SD Fsc 2 0x4E
SD Fsc 3 0x4F
is a block diagram of the SDI transmitter. The ICS664-02 frequency synthesizer
HD mode: 74.25 MHz or74.1578 MHz
SD mode: 54 MHz
10
Y
10
HD Line
10
C
Number
10
11
line
Insertion
num
SD
EDH
10 10
Processor
Clock
Enable
Generator
Figure 6-3: SDI Transmitter Block Diagram
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Value
0x09
0x2A
10
HD-SDI 20
CRC
10
Scrambler
Insertion
4X Bit
10 20
SD-SDI
Replicate
Scrambler
hd_sd
Description
REFCLK
TXUSRCLK
TXUSRCLK2
SDI Cable
Driver SDI Out
TXP
TXN
RocketIO
20
TXDATA
ug235_ch5_03_111405
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
R