Scc Interrupt Control Register - Motorola MVME162FX Programmer's Reference Manual

MC2 Chip

SCC Interrupt Control Register

ADR/SIZ
3
BIT
NAME
OPER
RESET
3-24
23 22 21
INT
R R R
0 0 0 PL
IL2-IL0 These three bits select the interrupt level for the SCC
controller. Level 0 does not generate an interrupt.
IEN When this bit is set high, the interrupt is enabled.
The interrupt is disabled when this bit is low.
INT This bit reflects the state of the INT pin from the
Z85230 controller (qualified by the IEN bit). When
this bit is high, an SCC controller interrupt is being
generated at the level programmed in IL2-IL0. When
the interrupt is cleared in the Z85230, INT returns to
zero.
$FFF4201C (8 bits)
20 19
IEN
R/W R R/W
0 PL 0 0 PL
18 17 16
IL2 IL1 IL0
R/W R/W
0 PL 0 PL