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MC2 Chip
3
3-22
These three bits select the interrupt level for the tick
IL2-IL0
timers. Level 0 does not generate an interrupt.
Writing a logic 1 to this bit clears the tick timer
ICLR
interrupt (i.e., INT bit in this register). This bit is
always read as zero.
When this bit is set high, the interrupt is enabled.
IEN
The interrupt is disabled when this bit is low.
When this bit is high, a tick timer interrupt is being
INT
generated at the level programmed in IL2-IL0 (if
nonzero). This bit is edge-sensitive and can be
cleared by writing a logic 1 into the ICLR control bit.
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