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IP2 Chipming Model
4
Pacer Clock
4-6
Notes 1. This column is a measure of IndustryPack
bandwidth for back to back cycles for a local bus master
which is accessing a memory or I/O space location on
an IndustryPack. It assumes a zero wait state
acknowledge reply from the IndustryPack.
2. This column is a measure of IndustryPack
bandwidth for DMA burst cycles between a local bus
slave and a memory or I/O space location on an
IndustryPack. It assumes a zero wait state
acknowledge reply from the IndustryPack.
3. This column is a measure of IndustryPack
bandwidth for DMA single cycles between a local bus
slave and a memory or I/O space location on an
IndustryPack. It assumes a zero wait state
acknowledge reply from the IndustryPack.
4. Burst mode sDMA is not supported when both bus
frequencies are 32 MHz.
5.: Because the specified band width assumes a zero
wait state IndustryPack cycle, it would be difficult to
achieve the stated bandwidths for an IP bus frequency
of 32 MHz.
The IP2 chip implements a general purpose pacer clock output for
external connection to the IndustryPacks. This feature complies
with the STROBE function defined in the IndustryPack
specification. The pacer clockÕs clock source is the MC68040 bus
clock. This clock input is fed through an 8-bit programmable pre-
scaling counter whose output is fed to a 16-bit counter. The 16-bit
counter increments at rising edges of the output of the pre-scale
logic and clears every time it reaches the value programmed into
the 16-bit pacer timer register. Depending on its programmed
mode, the pacer clock output either pulses or toggles each time the
16-bit counter matches and clears. Additional control bits in the
pacer clock control register allow software to stop, start, clear, and
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