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DMAC Control Register 2 (bits 0-7)
ADR/SIZ
BIT
7
NAME
OPER
RESET
This portion of the control register is loaded by the processor or the
DMAC when it loads the command word from the command
packet. Because this byte is loaded from the command packet in the
command chaining mode, the descriptions here also apply to the
control word in the command packet.
VME AM
BLK
$FFF40034 (8 bits of 32)
6
5
BLK
R/W
0 PS
These bits define the address modifier codes the
DMAC drives on the VMEbus when it is bus master.
During non-block transfer cycles, bits 0-5 define the
VMEbus address modifiers. During block transfers,
bits 2-5 define VMEbus address modifier bits 2-5,
and address modifier bits 0 and 1 are provided by
the DMAC to indicate a block transfer. Block
transfer mode should not be set in the address
modifier codes. The special block transfer bits
should be set to enable block transfers. If non-block
cycles are required to reach a 32- or 64-bit boundary,
bits 0 and 1 are used during these cycles.
These bits control the block transfer modes of the
DMAC:
0
Block transfers disabled
1
The DMAC executes D32 block transfer
cycles on the VMEbus. In the block transfer
mode, the DMAC may execute byte and two-
byte cycles at the beginning and ending of a
transfer in non-block transfer mode. If the
D16 bit is set, the DMAC executes D16 block
transfers.
Block transfers disabled
2
LCSR Programming Model
4
3
2
VME AM
R/W
0 PS
2
1
0
2-59
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