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MC2 Chip
Functional Description
3
MC2 chip Initialization
Flash and EPROM Interface
3-2
The following sections provide an overview of the functions
provided by the MC2 chip. A detailed programming model for the
MC2 chip control and status registers is provided in a later section.
The MC2 chip ASIC is designed to accommodate several memory
configurations and MVME162FX population versions. A
factory-programmed resident device is used to initialize the
MVME162FX Version Register, General Purpose Inputs Register,
and DRAM/SRAM Options Register (read only). A different
initialization device is used for each version of the MVME162FX.
Refer to the Programming Model on page 3-11.
The MC2 chip interfaces the MC68040 local bus to one 1M x 8 Intel
28F008SA and a 32-pin PLCC JEDEC standard EPROM. The Flash
and EPROM memory map locations can be swapped based upon a
jumper (J22, pins 9 and 10, GPIO3) input to the initialization PAL.
(The initialization device was discussed in the previous section.)
This enables the MVME162FX to execute reset code from either the
EPROM or Flash.
Note that MVME162FX models ordered without the VMEbus
interface are shipped with Flash memory blank (the factory uses the
VMEbus to program the Flash memory with debugger code). To
use the 162Bug package, MVME162Bug, in such models, be sure
that jumper header J22 is configured for the EPROM memory map.
Refer to Chapters 3 and 4 of the MVME162FX Installation and Use
documentation, V162FXA, for further details.
The MC2 chip executes multiple cycles to the eight-bit
Flash/EPROM devices so that byte, word, or longword accesses are
allowed. Burst accesses to Flash/EPROM are inhibited by the
interface so that they are broken into four longword accesses.
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