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Functional Blocks
The alternate address register also provides the upper eight bits of
2
the local address when the VMEbus slave cycle is A24.
The local bus master requests the local bus and executes cycles as
required. To reduce local bus loading and improve performance it
always attempts to transfer data using a burst transfer as defined by
the MC68040.
When snooping is enabled, the local bus master requests the cache
controller in the MC68040 to monitor the local bus addresses.
Local Bus to VMEbus DMA Controller
The DMA Controller (DMAC) operates in conjunction with the
local bus master, the VMEbus master, and a 16 four-byte FIFO
buffer. The DMA controller has a 32-bit local address counter, 32-bit
table address counter, a 32-bit VMEbus address counter, a 32-bit
byte counter, and control and status registers. The Local Control
and Status Register (LCSR) provides software with the ability to
control the operational modes of the DMAC. Software can program
the DMAC to transfer up to 4GB of data in the course of a single
DMA operation. The DMAC supports transfers from any local bus
address to any VMEbus address. The transfers may be from one
byte to 4GB in length.
To optimize local bus use, the DMAC automatically adjusts the size
of individual data transfers until 32-bit transfers can be executed.
Based on the address of the first byte, the DMAC transfers a
single-byte, a double-byte, or a mixture of both, and then continues
to execute quad-byte block transfer cycles. When the DMAC is set
for 64-bit transfers, the octal-byte transfers takes place. Based on the
address of the last byte, the DMAC transfers a single-byte, a
double-byte, or a mixture of both to end the transfer.
Using control register bits in the LCSR, the DMAC can be
configured to provide the following VMEbus capabilities:
Addressing capabilities: A16, A24, A32
2-11
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