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Functional Description
Local Bus to IndustryPack DMA Controllers
The IP2 supports two basic types of DMA cycles: Òstandard DMAÓ
(sDMA) and Òaddressed DMAÓ (aDMA). sDMA cycles are
requested by the IP. When the DMA controller (DMAC) detects a
DMA request and if that DMA controller is enabled, it will
acknowledge the request by transferring data between the local bus
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and the I/O space of the requesting IP device. Alternatively, aDMA
transfers are not linked to a request/acknowledge protocol. aDMA
cycles are initiated by the DMA controller as soon as its control
registers have been initialized by the MC68040. It will transfer data
between the local bus and a selected IP module memory space. The
IP2 chip implements four DMA controllers which can operate in the
sDMA or aDMA mode. The DMA controllers can be configured so
one is controller attached to each of the four possible IndustryPack
interfaces or so that DMA controllers a and b are attached to IP_a
and controllers c and d are attached to IP_c. The DMA controllers
support 8-, 16-, and 32-bit IndustryPack widths. The four DMA
channels can operate concurrently.
Each DMA controller has a 32-bit local address counter, a 32-bit
table address counter, a 24-bit byte counter, control registers, status
registers, and a 24-bit IP address counter. The data path for each
DMA controller passes through a FIFO which is eight locations
deep and four bytes wide.
sDMA transfers and byte count parameters must accommodate the
I/O port width. If the port width is 16 bits, then the byte count must
be initialized to an even value; if the width is 32 bits, then the byte
count must be set to a value which is a multiple of four. This implies
that transfer to I/O space under DMA control will always be the
same size as the port width. The IP address register must be
initialized to 0 before sDMA is enabled. This counter is used to align
data in the IP2 Chip.
The data has no alignment restrictions as it is moved to or from the
memory on the local bus. This would typically be DRAM on the
MC68040 local bus, but it could also be memory on the VMEbus.
To optimize local bus use when the IndustryPack is less than 32 bits
wide, the FIFO converts 8-bit and 16-bit IP transfers to 32-bit local
bus transfers. The FIFO data path logic also aligns data if the source
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