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Once a DMAC is enabled, its counter and control registers should
not be modified by software. When the command chaining mode is
used, the list of commands must be in local (not IP), 32-bit memory
and the entries must be aligned to a 16-byte boundary. That is, the
address which is loaded into the DMA table address counter must
have bits three through zero set to a zero. This is true for the initial
value which is loaded by the processor or the subsequent values
which are loaded by the command chaining logic. If they are not set
to zero, the command chaining process will halt.
A DMAC command packet includes a control word that defines:
single command interrupt enable, DMA transfer direction, and
DMAEND direction and usage. The format of the control word is
the same as control register 2. The command packet also includes a
local bus address, an IP address, a byte count, and a pointer to the
next command packet in the list. The end of a command is indicated
by setting bit 0 or 1 of the next command address. The command
packet format is shown in the following table.
Entry
0(bits 23-16)
1(Bits 31-0)
2(Bits 23-0)
3(Bits 23-0)
DMA Enable Function
There are certain DMA channel contexts which are illegal. If an
attempt is made to program the DMA control register 1 for each
channel a and b or c and d to an illegal state, the DEN (DMA enable
control bit) will not set when it is loaded to a one via a processor
store instruction. This condition can be tested by writing the DEN
bit to a one and reading a zero. Refer to the description of the DMA
Enable Register for the required programming sequence of the
control registers and enable bits.
Address of Next Command Packet
Control Word
Programming Model
Function
Local Bus Address
Byte Count
IndustryPack Address DMA
4
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