Dram/Sram Options Register; Table 3-5. Dram Size Control Bit Encoding - Motorola MVME162FX Programmer's Reference Manual

DRAM/SRAM Options Register

Note that this register is read only and is initialized at reset.
ADR/SIZ
BIT 23
NAME BEQ1
R
OPER
RESET
DZ2-DZ0
$FFF42024 (8 bits)
22 21
F1 F0
R R
Application SpeciÞc
DZx bits indicate the size and architecture of the
DRAM array. Software must initialize the DRAM
Space Size Register ($FFF42024 bits 26 - 24) based on
the value of DZ2 - DZ0. DZ2 -DZ0 are initialized at
reset to a value which is determined by the contents
of a factory-programmed resident device.

Table 3-5. DRAM Size Control Bit Encoding

DZ2 - DZ0
$0 1MB with 4-Mbit DRAMs
$1 2MB with 4-Mbit DRAMs
(Memory mezzanine is not available for this setting)
$3 4MB with 4-Mbit DRAMs (interleaved)
$4 4MB with 16-Mbit DRAMs
(Memory mezzanine is not available for this setting)
$5 8MB with 16-Mbit DRAMs
$6 DRAM mezzanine is not present
$7 16MB with 16-Mbit DRAMs (interleaved)
(Memory mezzanine is not available for this setting)
20 19 18
SZ1 SZ0 DZ2
R R R
DRAM ConÞguration
Programming Model
17 16
DZ1 DZ0
R R
3-29
3