Prom Decoder, Sram And Dma Control Register - Motorola MVME162FX Programmer's Reference Manual

VMEchip2

PROM Decoder, SRAM and DMA Control Register

2
ADR/SIZ
BIT
NAME
OPER
RESET
2-54
$FFF40030 (8 bits [6 used] of 32)
23 22 21
WAIT RMW
R/W
0 PSL
This register controls the snoop control bits used by the DMAC
when it is accessing table entries.
SRAMS These VMEchip2 bits are not used on the
MVME162FX.
TBLSC These bits control the snoop signal lines on the local
bus when the DMAC is table walking.
0
1
2
3
ROM0 This VMEchip2 bit is not used on the MVME162FX.
Its function is performed by the ROM0 bit in the
PROM Access Time Control Register in the MC2
chip. Refer to Chapter 3.
WAIT RMW This function is not used on the MVME162FX.
20 19
ROM0 TBLSC
R/W R/W
1 PSL 0 PS
Snoop inhibited
Write - Sink data
Read - Supply dirty data and leave dirty
Write - Invalidate
Read - Supply dirty data and mark invalid
Snoop inhibited
18 17 16
SRAMS
R/W
0 PS