82596Ca Lanc Interrupt Control Register - Motorola MVME162FX Programmer's Reference Manual

82596CA LANC Interrupt Control Register

ADR/SIZ
15
BIT
NAME PLTY
OPER R/W
RESET 0 PL
IL2-IL0
ICLR
IEN
INT
E/L*
PLTY
$FFF42028 (8 bits)
14 13 12
E/L* INT IEN
R/W R R/W
0 PL 0 PL 0 PL
Interrupt Request Level. These three bits select the
interrupt level for the 82596CA LANC. Level 0 does
not generate an interrupt.
In edge-sensitive mode, writing a logic 1 to this bit
clears the INT status bit. This bit has no function in
level-sensitive mode. This bit is always read as zero.
Interrupt Enable. When this bit is set high, the
interrupt is enabled. The interrupt is disabled when
this bit is low.
This status bit reflects the state of the INT pin from
the LANC (qualified by the IEN bit). When this bit is
high, a LANC INT interrupt is being generated at
the level programmed in IL2-IL0.
Edge or Level. When this bit is high, the interrupt is
edge-sensitive. The interrupt is level-sensitive when
this bit is low.
Polarity. When this bit is low, interrupt is activated
by a rising edge/high level of the LANC INT pin.
When this bit is high, interrupt is activated by a
falling edge/low level of the LANC INT pin. Note
that if this bit is changed while the E/L* bit is set (or
is being set), a LANC interrupt may be generated.
This can be avoided by setting the ICLR bit during
write cycles that change the E/L* bit.
Programming Model
11 10 9
IICLR IL2 IL1
C R/W R/W
0 0 PL 0 PL
3
8
IL0
R/W
0 PL
3-33