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Notes 1. For a complete description of the register bits, refer to
Detailed I/O Memory Maps
Tables 1-4 through 1-13 give the detailed memory maps for:
the data sheet for the specific chip. For a more detailed
memory map, refer to the following detailed peripheral
device memory maps.
2. The SCC is an 8-bit device located on an MC2 chip
private data bus. Byte access is required.
The data register of the Zilog Z85230 device which is
interfaced by the MC2 chip ASIC cannot be accessed.
The Zilog Z85230 has an indirect access mode to the
data registers which is functional and must be used.
3. Writes to the LCSR in the VMEchip2 must be 32 bits.
LCSR writes of 8 or 16 bits terminate with a TEA signal.
Writes to the GCSR may be 8, 16 or 32 bits. Reads to the
LCSR and GCSR may be 8, 16 or 32 bits. Byte reads
should be used to read the interrupt vector.
4. This area does not return an acknowledge signal. If
the local bus timer is enabled, the access times out and
is terminated by a TEA signal.
5. Size is approximate.
6. Port commands to the 82596CA must be written as
two 16-bit writes: upper word first and lower word
second.
7. Refer to the Flash and PROM Interface section in the
MC2 chip description in Chapter 3.
1-4
VMEchip2
1-5
MC2 chip
1-6
IP2 chip
1-7
IP2 chip Control and Status
Registers
Memory Maps
1-13
1
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