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IP2 Chipming Model
Programming Model
4
4-10
This section defines the programming model for the control and
status registers (CSRs) in the IP2 chip. The base address of the CSRs
is hardwired to $FFFBC000.
The possible operations for each bit in the CSR are as follows:
R
This bit is a read-only status bit.
R/W
This bit is readable and writable.
R/C
This status bit is cleared by writing a one to it.
C
Writing a zero to this bit clears this bit or another bit. This
bit reads as zero.
S
Writing a one to this bit sets this bit or another bit. This bit
reads as zero.
The possible states of the bits after assertion of the RESET* pin
(powerup reset or any local reset) are as defined below.
R
The bit is affected by reset.
X
The bit is not affected by reset.
A summary of the IP2 chip CSR registers is shown in Table 4-3. The
CSR registers can be accessed as bytes, words, or longwords. They
should not be accessed as lines. They are shown in the table as
bytes, and the bits in most of the following register descriptions are
labeled as bits 7 through 0.
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