Vector Base Register - Motorola MVME162FX Programmer's Reference Manual

IP2 Chipming Model
ADR/SIZ
BIT
NAME
OPER
RESET
4

Vector Base Register

ADR/SIZ
BIT
NAME
OPER
RESET
!
Caution
4-18
7 6
REV7 REV6 REV5
R R R
0 0
7 6
IV7 IV6 IV5
R/W R/W R/W
0 0
The interrupt Vector Base Register is an 8-bit read/write register
that is used to supply the vector to the CPU during an interrupt
acknowledge cycle for the four DMA controller interrupts and for
the pacer clock interrupt. Only the most significant five bits are
used. The least significant three bits encode the interrupt source
during the acknowledge cycle. The exception to this is that after
reset occurs, the interrupt vector passed is $07, which remains in
effect until a write is generated to the Vector Base Register.
Note Note that this register does not affect the vector
supplied during an interrupt acknowledge cycle for
any of the eight IndustryPack IRQ*s.
For some versions of the IP2 chip, this register is write
only. There is NO known workaround for this error.
This register does return the correct value for the
interrupt acknowledge cycle.
$FFFBC001 (8 bits)
5 4 3
REV4 REV3
R R
0 0 0
$FFFBC003 (8 bits)
5 4 3
IV4 IV3
R/W R/W
0 0 1
2 1 0
REV2 REV1 REV0
R R R
0 0 1
2 1 0
IV2 IV1 IV0
R R R
1 1 1