Motorola MVME162-460 Manuals

Manuals and User Guides for Motorola MVME162-460. We have 1 Motorola MVME162-460 manual available for free PDF download: Programmer's Reference Manual

Motorola MVME162-460 Programmer's Reference Manual

Motorola MVME162-460 Programmer's Reference Manual (320 pages)

Embedded Controller

Brand: Motorola | Category: Controller | Size: 2.27 MB

Table of Contents

Table of Contents
11
Chapter 1 Board Description and Memory Maps

24
- Introduction
  25
- Requirements
  25
- Features
  25
- Block Diagram
  27
- Functional Description
  27
- Figure 1-1. MVME162FX Block Diagram
  27
- No-Vmebus-Interface Option
  28
- Table 1-1. Redundant Functions in the Vmechip2 and MC2 Chip
  28
- Vmebus Interface and Vmechip2
  29
- Memory Maps
  30
- Local Bus Memory Map
  30
- Normal Address Range
  30
- Table 1-2. Local Bus Memory Map
  31
- Table 1-3. Local Bus I/O Devices Memory Map
  33
- Detailed I/O Memory Maps
  35
- Table 1-4. Vmechip2 Memory Map (Sheet 1 of 3)
  37
- Table 1-4. Vmechip2 Memory Map (Sheet 2 of 3)
  39
- Table 1-4. Vmechip2 Memory Map (Sheet 3 of 3)
  42
- Table 1-5. MC2 Chip Register Map
  43
- Table 1-6. IP2 Chip Overall Memory Map
  44
- Table 1-7. IP2 Chip Memory Map - Control and Status Registers
  45
- Table 1-8. Z85230 SCC Register Addresses
  52
- Table 1-9. 82596CA Ethernet LAN Memory Map
  52
- BBRAM/TOD Clock Memory Map
  53
- Table 1-10. 53C710 SCSI Memory Map
  53
- Table 1-11. MK48T08 BBRAM/TOD Clock Memory Map
  54
- Table 1-13. TOD Clock Memory Map
  55
- Interrupt Acknowledge Map
  59
- Vmebus Memory Map
  59
- Vmebus Accesses to the Local Bus
  59
- Vmebus Short I/O Memory Map
  59
- Software Support Considerations
  60
- Interrupts
  60
- Cache Coherency
  60
- Sources of Local BERR
  61
- Local Bus Time-Out
  61
- Vmebus Access Time-Out
  61
- Vmebus BERR
  61
- Local DRAM Parity Error
  62
- Vmechip2
  62
- Bus Error Processing
  62
- Description of Error Conditions on the MVME162FX
  63
- MPU Parity Error
  63
- MPU Off-Board Error
  63
- MPU TEA - Cause Unidentified
  64
- MPU Local Bus Time-Out
  64
- DMAC Vmebus Error
  65
- DMAC Parity Error
  65
- DMAC Off-Board Error
  66
- DMAC LTO Error
  66
- DMAC TEA - Cause Unidentified
  67
- LAN Parity Error
  67
- LAN Off-Board Error
  68
- LAN LTO Error
  68
- SCSI Parity Error
  68
- SCSI Off-Board Error
  69
- SCSI LTO Error
  69
- Example of the Proper Use of Bus Timers
  70
- MVME162FX MC68040 Indivisible Cycles
  71
- Illegal Access to IP Modules from External Vmebus Masters
  72
- Introduction
  73
- Summary of Major Features
  73
- Functional Blocks
  76
- Local Bus to Vmebus Interface
  76
- Figure 2-1. Vmechip2 Block Diagram
  77
- Local Bus to Vmebus Requester
  80
- Vmebus to Local Bus Interface
  81
- Local Bus to Vmebus DMA Controller
  83
- No Address Increment DMA Transfers
  85
- DMAC Vmebus Requester
  86
- Tick and Watchdog Timers
  87
- Prescaler
  87
- Tick Timers
  88
- Watchdog Timer
  89
- Vmebus Interrupter
  89
- Vmebus System Controller
  90
- Arbiter
  90
- IACK Daisy-Chain Driver
  91
- Bus Timer
  91
- Reset Driver
  91
- Local Bus Interrupter and Interrupt Handler
  92
- Global Control and Status Registers
  94
- LCSR Programming Model
  94
- Table 2-1. Vmechip2 Memory Map - LCSR Summary (Sheet 1 of 2)
  96
- Table 2-1. Vmechip2 Memory Map - LCSR Summary (Sheet 2 of 2)
  98
- Programming the Vmebus Slave Map Decoders
  100
- Vmebus Slave Ending Address Register 1
  103
- Vmebus Slave Starting Address Register 1
  103
- Vmebus Slave Ending Address Register 2
  103
- Vmebus Slave Starting Address Register 2
  104
- Vmebus Slave Address Translation Address Offset Register 1
  104
- Vmebus Slave Address Translation Select Register 1
  105
- Vmebus Slave Address Translation Address Offset Register 2
  106
- Vmebus Slave Address Translation Select Register 2
  106
- Vmebus Slave Write Post and Snoop Control Register 2
  107
- Vmebus Slave Address Modifier Select Register 2
  108
- Vmebus Slave Write Post and Snoop Control Register 1
  109
- Programming the Local Bus to Vmebus Map Decoders
  111
- Local Bus Slave (Vmebus Master) Ending Address Register 1
  114
- Local Bus Slave (Vmebus Master) Ending Address Register 2
  114
- Local Bus Slave (Vmebus Master) Starting Address Register 2
  114
- Local Bus Slave (Vmebus Master) Ending Address Register 3
  114
- Local Bus Slave (Vmebus Master) Starting Address Register 3
  115
- Local Bus Slave (Vmebus Master) Ending Address Register 4
  115
- Local Bus Slave (Vmebus Master) Starting Address Register 4
  115
- Local Bus Slave (Vmebus Master) Address Translation Select Register 4
  117
- Local Bus Slave (Vmebus Master) Attribute Register 4
  117
- Local Bus Slave (Vmebus Master) Attribute Register 3
  118
- Local Bus Slave (Vmebus Master) Attribute Register 1
  118
- Vmebus Slave GCSR Group Address Register
  120
- Vmebus Slave GCSR Board Address Register
  120
- Local Bus to Vmebus Enable Control Register
  121
- Local Bus to Vmebus I/O Control Register
  122
- ROM Control Register
  123
- Programming the Vmechip2 DMA Controller
  124
- DMAC Registers
  125
- Table 2-2. DMAC Command Table Format
  125
- PROM Decoder, SRAM and DMA Control Register
  126
- Local Bus to Vmebus Requester Control Register
  127
- DMAC Control Register 1 (Bits 0-7)
  128
- DMAC Control Register 2 (Bits 8-15)
  129
- DMAC Control Register 2 (Bits 0-7)
  131
- DMAC Local Bus Address Counter
  132
- DMAC Vmebus Address Counter
  133
- DMAC Byte Counter
  133
- Vmebus Interrupter Control Register
  134
- Vmebus Interrupter Vector Register
  135
- MPU Status and DMA Interrupt Count Register
  136
- DMAC Status Register
  137
- Programming the Tick and Watchdog Timers
  138
- Vmebus Arbiter Time-Out Control Register
  138
- DMAC Ton/Toff Timers and Vmebus Global Time-Out Control Register
  139
- VME Access, Local Bus, and Watchdog Time-Out Control Register
  140
- Prescaler Control Register
  141
- Tick Timer 1 Compare Register
  142
- Tick Timer 1 Counter
  142
- Tick Timer 2 Compare Register
  143
- Tick Timer 2 Counter
  143
- Tick Timer 2 Compare Register
  144
- Tick Timer 2 Counter
  144
- Board Control Register
  145
- Watchdog Timer Control Register
  146
- Tick Timer 2 Control Register
  147
- Tick Timer 1 Control Register
  148
- Prescaler Counter
  148
- Programming the Local Bus Interrupter
  149
- Table 2-3. Local Bus Interrupter Summary
  150
- Local Bus Interrupter Status Register (Bits 24-31)
  152
- Local Bus Interrupter Status Register (Bits 16-23)
  153
- Local Bus Interrupter Status Register (Bits 8-15)
  154
- Local Bus Interrupter Status Register (Bits 0-7)
  155
- Local Bus Interrupter Enable Register (Bits 24-31)
  156
- Local Bus Interrupter Enable Register (Bits 16-23)
  157
- Local Bus Interrupter Enable Register (Bits 8-15)
  158
- Local Bus Interrupter Enable Register (Bits 0-7)
  159
- Software Interrupt Set Register (Bits 8-15)
  160
- Interrupt Clear Register (Bits 24-31)
  160
- Interrupt Clear Register (Bits 16-23)
  161
- Interrupt Clear Register (Bits 8-15)
  162
- Interrupt Level Register 1 (Bits 24-31)
  162
- Interrupt Level Register 1 (Bits 16-23)
  163
- Interrupt Level Register 1 (Bits 8-15)
  163
- Interrupt Level Register 1 (Bits 0-7)
  164
- Interrupt Level Register 2 (Bits 24-31)
  164
- Interrupt Level Register 2 (Bits 16-23)
  165
- Interrupt Level Register 2 (Bits 8-15)
  165
- Interrupt Level Register 2 (Bits 0-7)
  166
- Interrupt Level Register 3 (Bits 24-31)
  166
- Interrupt Level Register 3 (Bits 16-23)
  167
- Interrupt Level Register 3 (Bits 8-15)
  167
- Interrupt Level Register 3 (Bits 0-7)
  168
- Interrupt Level Register 4 (Bits 24-31)
  168
- Interrupt Level Register 4 (Bits 16-23)
  169
- Interrupt Level Register 4 (Bits 0-7)
  170
- Vector Base Register
  170
- I/O Control Register 1
  171
- I/O Control Register 2
  172
- I/O Control Register 3
  172
- Miscellaneous Control Register
  172
- GCSR Programming Model
  175
- Programming the GCSR
  177
- Table 2-4. Vmechip2 Memory Map (GCSR Summary)
  178
- Vmechip2 Revision Register
  179
- Vmechip2 ID Register
  179
- Vmechip2 LM/SIG Register
  179
- Vmechip2 Board Status/Control Register
  181
- Introduction
  185
- Summary of Major Features
  185
- Functional Description
  186
- MC2 Chip Initialization
  186
- Flash and EPROM Interface
  186
- BBRAM Interface
  187
- 82596CA LAN Interface
  187
- MPU Port and MPU Channel Attention
  187
- MC68040-Bus Master Support for 82596CA
  188
- LANC Bus Error
  189
- LANC Interrupt
  189
- 53C710 SCSI Controller Interface
  189
- SRAM Memory Controller
  190
- DRAM Memory Controller
  190
- Table 3-1. DRAM Performance
  190
- Z85230 SCC Interface
  191
- Tick Timers
  192
- Watchdog Timer
  192
- Local Bus Timer
  193
- Memory Map of the MC2 Chip Registers
  193
- Table 3-2. MC2 Chip Register Map
  194
- Programming Model
  195
- MC2 Chip ID Register
  195
- MC2 Chip Revision Register
  196
- General Control Register
  196
- Interrupt Vector Base Register
  198
- Table 3-3. Interrupt Vector Base Register Encoding and Priority
  199
- Programming the Tick Timers
  200
- Tick Timer 1 and 2 Compare and Counter Registers
  200
- LSB Prescaler Count Register
  202
- Prescaler Clock Adjust Register
  202
- Tick Timer Interrupt Control Registers
  205
- DRAM Parity Error Interrupt Control Register
  207
- SCC Interrupt Control Register
  208
- Tick Timer 4 Control Register
  209
- Tick Timer 3 Control Register
  209
- DRAM and SRAM Memory Controller Registers
  210
- DRAM Space Base Address Register
  210
- SRAM Space Base Address Register
  211
- DRAM Space Size Register
  212
- Table 3-4. DRAM Size Control Bit Encoding
  212
- DRAM/SRAM Options Register
  213
- Table 3-5. DRAM Size Control Bit Encoding
  213
- Table 3-6. SRAM Size Control Bit Encoding
  214
- SRAM Space Size Register
  215
- Table 3-7. SRAM Size Control Bit Encoding
  215
- LANC Error Status Register
  216
- 82596CA LANC Interrupt Control Register
  217
- LANC Bus Error Interrupt Control Register
  218
- SCSI Error Status Register
  219
- General Purpose Inputs Register
  220
- MVME162FX Version Register
  221
- SCSI Interrupt Control Register
  222
- Tick Timer 3 and 4 Compare and Counter Registers
  223
- Bus Clock Register
  224
- EPROM Access Time Control Register
  225
- Flash Parameter Register
  226
- ABORT Switch Interrupt Control Register
  227
- RESET Switch Control Register
  228
- Watchdog Timer Control Register
  229
- Access and Watchdog Time Base Select Register
  230
- DRAM Control Register
  231
- MPU Status Register
  233
- 32-Bit Prescaler Count Register
  234
- Introduction
  235
- Summary of Major Features
  235
- Functional Description
  236
- General Description
  236
- Cache Coherency
  236
- Local Bus to Industrypack DMA Controllers
  237
- Clocking Environments and Performance
  239
- Table 4-1. IP2 Chip Clock Cycles
  239
- Pacer Clock
  240
- Error Reporting
  241
- Error Reporting as a Local Bus Slave
  241
- Error Reporting as a Local Bus Master
  241
- Industrypack Error Reporting
  241
- Interrupts
  242
- Overall Memory Map
  243
- Table 4-2. IP2 Chip Overall Memory Map
  243
- Programming Model
  244
- Table 4-3. IP2 Chip Memory Map - Control and Status Registers
  245
- Chip ID Register
  251
- Chip Revision Register
  251
- Vector Base Register
  252
- Ip_A, Ip_B, Ip_C, Ip_D Memory Base Address Registers
  253
- Ip_A or Double Size Ip_Ab Memory Base Address Registers
  254
- Ip_B Memory Base Address Registers
  254
- Ip_C or Double Size Ip_Cd Memory Base Address Registers
  255
- Ip_D Memory Base Address Registers
  255
- Ip_A, Ip_B, Ip_C, Ip_D Memory Size
  256
- Registers
  257
- IP Clock Register
  263
- DMA Arbitration Control Register
  264
- IP RESET Register
  265
- Programming the DMA Controllers
  265
- DMA Enable Function
  267
- DMA Control and Status Register Set Definition
  268
- Programming the Pacer Clock
  278
- Local Bus to Industrypack Addressing
  281
- 8-Bit Memory Space
  281
- 16-Bit Memory Space
  282
- 32-Bit Memory Space
  283
- Ip_A I/O Space
  284
- Ip_Ab I/O Space
  285
- Ip_A ID Space
  286
- IP to Local Bus Data Routing
  287
- Memory Space Accesses
  287
- Serial Port Connections
  291
- Introduction
  291
- Introduction
  293
- Figure 5-1. MVME162FX Port 1 EIA-232 DCE, MVME712M Port 2 DTE
  293
- Figure 5-2. MVME162FX Port 1 EIA-232 DCE, MVME712M Port
  294
- Figure 5-3. MVME162FX Port 2 EIA-232 DTE, MVME712M Port 4 DTE
  295
- Figure 5-4. MVME162FX Port 2 EIA-232 DCE, MVME712M Port
  296
- Figure 5-5. MVME162FX Port 2 EIA-232 DTE, MVME712M Port
  297
- Figure 5-6. MVME162FX Port 2 EIA-232 DCE, MVME712M Port 4 DTE
  298
- Figure 5-7. MVME162FX Port 2 EIA-530
  299
- Figure 5-8. MVME162FX Port 2 EIA-530 DCE
  300
- Figure 5-9. MVME162FX Port 1 EIA-232 DCE
  301
- Figure 5-10. MVME162FX Port 1 EIA-232 DCE, MVME712AM/-13 Port 2 as Modem Port
  302
- Figure 5-11. MVME162FX Port 2 EIA-232 DTE
  303
- Figure 5-12. MVME162FX Port 2 EIA-232 DCE
  304
- Figure 5-13. MVME162FX EIA-485/EIA-422 Connections
  305
- Vmechip2 Tick Timer 1 Periodic Interrupt Example
  307

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