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GCSR Programming Model
GCSR Programming Model
2
This section describes the programming model for the Global
Control and Status Registers (GCSR) in the VMEchip2. The local
bus map decoder for the GCSR registers is included in the
VMEchip2. The local bus base address for the GCSR is $FFF40100.
The registers in the GCSR are 16 bits wide and they are byte
accessible from both the VMEbus and the local bus. The GCSR is
located in the 16-bit VMEbus short I/O space and it responds to
address modifier codes $29 or $2D. The address of the GCSR as
viewed from the VMEbus depends upon the GCSR group select
value XX and GCSR board select value Y programmed in the LCSR.
The board value Y may be $0 through $E, allowing 15 boards in one
group. The value $F is reserved for the location monitors.
The VMEchip2 includes four location monitors (LM0-LM3). The
location monitors provide a broadcast signaling capability on the
VMEbus. When a location monitor address is generated on the
VMEbus, all location monitors in the group are cleared. The signal
interrupts SIG0-SIG3 should be used to signal individual boards.
The location monitors are located in the VMEbus short I/O space
and the specific address is determined by the VMEchip2 group
address. The location monitors LM0-LM3 are located at addresses
$XXF1, $XXF3, $XXF5, and $XXF7 respectively. A location monitor
cycle on the VMEbus is generated by a read or write to VMEbus
short I/O address $XXFN, where XX is the group address and N is
the specific location monitor address. When the VMEchip2
generates a location monitor cycle to the VMEbus, within its own
group, the VMEchip2 DTACKs itself. A VMEchip2 cannot DTACK
location monitor cycles to other groups.
The GCSR section of the VMEchip2 contains the following registers:
a chip ID register, a chip revision register, a location monitor status
register, an interrupt control register, a board control register, and six
general purpose registers.
2-103
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