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Clock Budget
5,2,2,2
6,4,4,4
6,3,3,3
4,2,2,2
Note
Z85230 SCC Interface
The MC2 chip provides a map decoder and an interrupt handler for
the Zilog Z85230. The base address is $FFF45000. The MC2 chip
requests an interrupt at the level programmed in the SCC interrupt
control register if the interrupt is enabled and a low level is detected
on the SCC INT* pin. The Z85230 provides the interrupt vector for
the interrupt acknowledge cycle.
The MC2 chip supports as many as four Z85230 devices. (There is
only one Z85230 on the MVME162FX. Refer to the Board Level
Hardware Description in the MVME162FX Embedded Controller
Installation and Use manual.) The addresses for the devices are
defined as follows. Note that CSR bits were added to the General
Control Register to control the delay time for the Z85230 IACK
cycle.
Table 3-1. DRAM Performance
Interleaved, read, 32MHz, without TEA on parity error
Non-interleaved, read, 32MHz, with TEA on parity error
Interleaved, read, 32MHz, with TEA on parity error
Write, 32MHz
TEA is the MC68040 bus error transaction signal. ÒWith
TEAÓ indicates that a bus error cycle occurs if a DRAM
parity error was detected.
Address Range
$FFF45000 - $FFF453FF
$FFF45400 - $FFF457FF
$FFF45800 - $FFF45BFF
$FFF45C00 - $FFF45FFF
Functional Description
Operating Conditions
SCC Device Number
0
1
2
3
3
3-7
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