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Clocking Environments and Performance
The IP2 chip has two clock domains. The majority of the logic is
controlled by the MC68040 local bus clock which can be 25 MHz or
32 MHz. The IndustryPack interface is controlled by the
IndustryPack clock. The IndustryPack clock can be 8 MHz or set
equal to the local bus clock. When logic signals cross from one clock
domain to another, they must be synchronized to the new clock
frequency. The latency time due this synchronization is generally
hidden due to the FIFOs in the data path. However, there are two
functions where the latency time affects performance. One of them
is when a local bus master such at the MC68040 accesses an
IndustryPack resource, such as reading back to back memory
locations. One to two IP clock cycles of overhead is associated with
this function. The other is when arbitration logic must resolve
inputs from both clock domains to determine which IndustryPack
will be granted DMA service. There are two IP clock cycles of
overhead associated with this function. The following table
explains the effect of this latency for given clocking environments.
The bandwidth which is specified in the following table is the
available bandwidth to the IndustryPack bus. This bandwidth can
be split between one, two, three, or four IP modules.
Bus Frequency
MC68040
25 MHz
32 MHz
32 MHz
Table 4-1. IP2 chip Clock Cycles
Period and Bandwidth to 32-Bit IP Space
Back to Back
IP
Examine
(Note 1)
8 MHz
4 IP clocks
8 MB/sec
8 MHz
3 IP clocks
10.6 MB/sec
32 MHz
6 IP clocks
(Note 5)
21 MB/sec
Functional Description
Four Cycle
Single Cycle
DMA Burst
DMA
(Note 2)
(Note 3)
10 IP clocks
4 IP clocks
12.8 MB/sec
8 MB/sec
10 IP clocks
4 IP clocks
12.8 MB/sec
8 MB/sec
12 IP clocks
6 IP clocks
42 MB/sec
21 MB/sec
(Note 4)
4
4-5
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