Mvme162Fx Version Register - Motorola MVME162FX Programmer's Reference Manual

MVME162FX Version Register

The contents of a PAL and the state of an 8-position jumper block
are translated to bit settings of the General Purpose Inputs Register,
Version Register and DRAM/SRAM Options Register when the
MC2 chip is reset. These registers are read only. Writes to these
registers are terminated without exception but do not change their
contents.
ADR/SIZ
BIT 15
NAME V7
OPER R
RESET
V0
V1
V2
V3
V4
V5
V6
$FFF4202C (8 bits)
14 - 9
V6 - V1
R
Application SpeciÞc
V0 set to a one indicates that the processor and
associated logic is operating at 32 MHz. V0 set to a
zero indicates 25 MHz.
V1 set to a one indicates that the VMEchip2 ASIC is
not present. V1 set to a zero indicates that a VMEbus
interface is present.
If V1 is set to a zero, the MC2 chip local bus access
timer is inhibited.
V2 set to a one indicates that the SCSI interface is not
present. V2 set to a zero indicates that a SCSI
interface is present.
V3 set to a one indicates that the Ethernet interface is
not present. V3 set to a zero indicates that a Ethernet
interface is present.
V4 set to a one indicates that the MC68040 is present.
V4 set to a zero indicates that a MC68LC040 is
present.
This bit is not functional on the MC2 chip.
Reserved for internal use only. (V6 is set to a 0
indicating that the IP2 chip #2 is not present.)
Programming Model
8
V0
R
3-37
3