Dram Space Size Register; Table 3-4. Dram Size Control Bit Encoding - Motorola MVME162FX Programmer's Reference Manual

MC2 Chip

DRAM Space Size Register

ADR/SIZ
BIT
3
NAME
OPER
RESET
3-28
31 30 29
R/W R/W R/W
0 PL 0 PL 0 PL
DZ2-DZ0 The size bits configure the DRAM decoder for a
particular memory size. The following table defines
their encoding. Note that the table specifies the
allowed bit combinations for DZ2 - DZ0. Any other
combinations generate unpredictable results.
DZ2 - DZ0 are set equal to the DZ2 - DZ0 bits of the
DRAM/SRAM Options Register. Note that
changing DZ2-DZ0 so that the DRAM architecture
changes between interleaved and non-interleaved
relocates the data. DZ2 - DZ0 are programmable to
facilitate diagnostic software.

Table 3-4. DRAM Size Control Bit Encoding

DZ2 - DZ0
$0 1MB with 4-Mbit DRAMs
$1 2MB with 4-Mbit DRAMs
(Memory mezzanine is not available for this setting)
$3 4MB with 4-Mbit DRAMs (interleaved)
$4 4MB with 16-Mbit DRAMs
(Memory mezzanine is not available for this setting)
$5 8MB with 16-Mbit DRAMs
$6 DRAM mezzanine is not present.
$7 16MB with 16-Mbit DRAMs (interleaved)
(Memory mezzanine is not available for this setting)
$FFF42024 (8 bits)
28 27
DZ2
R/W R/W R/W
0 PL 0 PL 0 PL
Memory Size
26 25 24
DZ1 DZ0
R/W R/W
0 PL 0 PL