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IP RESET Register
ADR/SIZ
BIT
7
0
NAME
OPER
R
RESET
0 R
RES
Note
Programming the DMA Controllers
The IP2 chip implements four DMA channels. They can operate in
the standard or addressed mode. sDMA transfers must
accommodate the I/O port width. If the port width is 16 bits, then
the byte count must be even; if the width is 32 bits, then the byte
count must be a multiple of four bytes. The IP address counter must
be initialized to zero before an sDMA transfer is enabled. There are
no other restrictions placed on DMA operations.
$FFFBC01F (8 bits)
6
5
0
0
R
R
0 R
0 R
0 R
Setting RES to a one asserts the IP2 chip IPRESET*
signal. IPRESET* is intended to be connected to the
Reset* signal on all four IndustryPacks. When
software sets the RES bit, IPRESET* stays asserted
until software clears RES.
Unlike the IPIC used on earlier versions of the
MVME162, the IPRESET* is not asserted when the
RESET* in to the ASIC (board level reset) is asserted.
For board artwork marked 84-W90B01E or later, the
Reset signal to the IP bus is always driven with the
power-up Reset. The power-up Reset is combined
(ORed together) with the IPRESET* signal from the
IP2 ASIC.
The MVME162FX does not comply with the IP
specification regarding reset. The MVME162FX does
not monitor Vcc and assert reset if Vcc is below a
certain threshold.
Programming Model
4
3
2
0
0
0
R
R
R
0 R
0 R
1
0
0
RES
R
R
0 R
0 R
4-31
4
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