Motorola MVME162FX Programmer's Reference Manual page 274

IP2 Chipming Model
4
ADR/SIZ
BIT
NAME
OPER
RESET
4-40
DMA Control Register 2
This register is loaded by the processor or by DMA when it loads
the command word from the command packet. Because this
register is loaded from the command packet in the command
chaining mode, the descriptions here will also apply to the control
word in the command packet.
$FFFBC025, $3D, $55, $6D (8 bits each)
7 6
INTE 0 DMAEI
R R/W R/W
0 R 0 R 0 R
XXX,XXX These bits are not under software control. Reading
or writing to them has no effect on the operation of
the IP2 chip ASIC.
TOIP This bit defines the direction in which DMAC
transfers data. When this bit is high, data is
transferred to the IndustryPack. When it is low, data
is transferred from the IndustryPack.
ENTO ENTO set to a one will enable the watchdog timeout
function for DMA cycles on the IP bus. The timeout
period is fixed at approximately 1 msec. If a timeout
does occur, the IP bus cycle is terminated and the
IPTO bit is set in the DMA Status Register. Note that
the IndustryPack interface in the IP2 chip ASIC will
wait indefinitely if the ENTO bit is cleared and a
DMA cycle on the IP bus is not acknowledged. The
IP2 chip ASIC must be reset to clear this condition. It
is recommended that ENTO be set to a one.
5 4 3
DMAEO ENTO
R/W R/W
0 R 0 R
2 1 0
TOIP XXX XXX
R/W R/W R/W
0 R 0 R 0 R