Programming The Pacer Clock - Motorola MVME162FX Programmer's Reference Manual

IP2 Chipming Model

Programming the Pacer Clock

ADR/SIZ
4
BIT
NAME
OPER
RESET
4-44
Pacer clock registers are defined in the following paragraphs.
Pacer Clock Interrupt Control Register
7 6
0 IRE INT
R R/W R
0 R 0 R 0 R
IL2-0 These three bits select the interrupt level for the
pacer clock interrupt. Level 0 does not generate an
interrupt.
ICLR Writing a logic 1 to this bit clears the INT status bit.
This bit always reads as 0.
IEN When IEN is set, the pacer clock interrupt is enabled.
When IEN is cleared, the interrupt is disabled.
INT When this bit is high, an interrupt is being generated
for the pacer clock at the level programmed in
IL2-IL0.
IRE This bit controls which action of the pacer clock
output causes interrupts.
IRE
0
1
$FFFBC080 (8 bits)
5 4 3
IEN ICLR
R/W C
0 R 0 R
Pacer Clock Action That Causes Interrupts
Rising Edge
Falling Edge
2 1 0
IL2 IL1 IL0
R/W R/W R/W
0 R 0 R 0 R