Lanc Bus Error Interrupt Control Register - Motorola MVME162FX Programmer's Reference Manual

MC2 Chip

LANC Bus Error Interrupt Control Register

ADR/SIZ
3
BIT
NAME
OPER
RESET
3-34
7 6
SC1 SC0 INT
R/W R/W R
0 PL 0 PL 0 PL
IL2-IL0 Interrupt Request Level. These three bits select the
interrupt level for the 82596CA LANC bus error
condition. Level 0 does not generate an interrupt.
ICLR Writing a logic 1 into this bit clears the INT status bit.
This bit is always read as zero.
IEN Interrupt Enable. When this bit set high, the
interrupt is enabled. The interrupt is disabled when
this bit is low.
INT Interrupt Status. When this bit is high, a LANC Bus
Error interrupt is being generated at the level
programmed in IL2-IL0.
SC1-SC0 Snoop Control. These control bits determine the
value that the MC2 chip drives onto the local
MC68xx040 bus SC1 and SC0 pins, when the
82596CA (LANC) performs DMA accesses. During
LANC DMA, if bit SC0 is 0, local bus pin SC0 is low,
and when bit SC0 is 1, pin SC0 is high. The same
relationship holds true for bit and pin SC1. Refer to
the M68040 user's manual for details on how it uses
the snoop control signals.
$FFF42028 (8 bits)
5 4 3
IEN ICLR
R/W C
0 PL 0
2 1 0
IL2 IL1 IL0
R/W R/W R/W
0 PL 0 PL 0 PL