Vmebus Interrupter Control Register - Motorola MVME162FX Programmer's Reference Manual

VMEchip2
Table Address Counter
2
ADR/SIZ
BIT
NAME
OPER
RESET

VMEbus Interrupter Control Register

ADR/SIZ
BIT
NAME
OPER
RESET
2-62
31
In the command chaining mode, this counter should be loaded by
the processor with the starting address of the list of commands.
This register gets reloaded by the DMAC with the starting address
of the current command. The last command in a list should have
bits 0 and 1 set in the next command pointer.
$FFF40048 (8 bits [7 used] of 32)
31 30 29
IRQ1S
R/W
0 PS
This register controls the VMEbus interrupter.
IRQL These bits define the level of the VMEbus interrupt
generated by the VMEchip2. A VMEbus interrupt is
generated by writing the desired level to these bits.
These bits always read 0 and writing 0 to these bits
has no effect.
IRQS This bit is the IRQ status bit. When this bit is high,
the VMEbus interrupt has not been acknowledged.
When this bit is low, the VMEbus interrupt has been
acknowledged. This is a read-only status bit.
IRQC This bit is VMEbus interrupt clear bit. When this bit
is set high, the VMEbus interrupt is removed. This
feature is only used when the IRQ1 broadcast mode
$FFF40044 (32 bits)
. . .
Table Address Counter
R/W
0 PS
28 27
IRQC IRQS
S R
0 PS 0 PS
0
26 25 24
IRQL
S
0 PS