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DMAC TEA - Cause Unidentified
Description:
An error occurred while the DMAC was local bus master and
additional status was not provided.
MPU Notification:
DMAC interrupt (when enabled).
Status:
The DLBE bit is set in the DMAC Status Register (address
$FFF40048 bit 6).
Comments:
An 8- or 16-bit write to the LCSR in the VMEchip2 causes this error.
If the TBL bit is set (address $FFF40048 bit 2) the error occurred
during a command table access, otherwise the error occurred
during a data access.
LAN Parity Error
Note
Description:
Parity error while the LANCE was reading DRAM MPU.
Notification:
MC2 chip Interrupt (LAN ERROR IRQ).
Status:
MC2 chip LAN Error Status Register ($FFF42028).
Comments:
The LANCE has no ability to respond to TEA so the error interrupt
and status are provided in the MC2 chip. Control for the interrupt
is in the MC2 chip LAN Error Interrupt Control Register
($FFF4202B).
The present MVME162FX models do not contain parity
DRAM.
Software Support Considerations
1
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