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IP2 Chipming Model
Functional Description
4
General Description
Cache Coherency
4IP2 Chipming Model
4-2
Recovery timer for each IndustryPack to provide dead time
between back to back accesses.
The following sections provide an overview of the functions
provided by the IP2 chip. A detailed programming model for the
IP2 chip control and status registers is provided in a later section of
this chapter.
The IP2 chip converts IP-bound MC68040 read/write/interrupt
acknowledge cycles to IndustryPack cycles. Control registers
within the IP2 chip control the assumed width of the IndustryPack
that is being accessed. The IP2 chip interfaces to four 16-bit
IndustryPack positions. The naming convention for single size
IndustryPack population of each of these positions is:
IndustryPack-a (IP_a), IndustryPack-b (IP_b), IndustryPack-c
(IP_c), and IndustryPack-d (IP_d). The naming convention for
double size IndustryPack population of these positions is
IndustryPack-a/b (IP_ab) and IndustryPack-c/d (IP_cd). (A double
size IndustryPack can occupy positions A and B, or it can occupy
positions C and D.)
The IP2 chip observes the snoop control (SC1, SC0) and memory
inhibit (MI*) signals to maintain cache coherency. When SC1, SC0
indicate that snooping is inhibited, the IP2 chip pair ignores the
memory inhibit (MI*) signal line. When SC1, SC0 do not indicate
that snooping is inhibited, the IP2 chip waits for the negation of MI*
before responding to a cycle. If TA* or TEA* is asserted by another
local bus slave before MI* is negated, then the IP2 chip assumes that
the cycle is over and that it is not to participate.
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