Motorola MVME162FX Programmer's Reference Manual page 270

IP2 Chipming Model
4
ADR/SIZ
BIT
NAME
OPER
RESET
4-36
bit was detected in the DMA Control Register 1. A
DMAC interrupt will be generated if interrupts are
enabled.
IPEND When this bit is set, the DMA process was
terminated if the DMAEND signal was asserted by
the Industry Pack and the DMAEI bit is set in the
DMA Control Register 2.This bit is cleared when
DMA is enabled. A DMAC interrupt will be
generated if interrupts are enabled
DMA Interrupt Control Register
$FFFBC021, $39, $51, $69 (8 bits each)
7 6
0 0 DINT
R R R
0 R 0 R 1 R
DIL2-DIL0 These three bits select the interrupt level for DMA.
Level 0 does not generate an interrupt.
DICLR Writing a logic 1 to this bit clears the DINT status bit.
DIEN When DIEN is set, the interrupt is enabled. When
DIEN is cleared, the interrupt is disabled.
DINT When this bit is high, an interrupt will be generated
for a DMAC if the DIEN bit is set to a one. The
interrupt is at the level programmed in DL2-DL0.
The DINT bit is set when one of the following bits
are set in the Status Register: DLBE, IPEND,
CHANI, IPTO, and DONE.
5 4 3
DIEN DICLR
R/W C
0 R 0 R
2 1 0
DIL2 DIL1 DIL0
R/W R/W R/W
0 R 0 R 0 R