Mpu Status Register - Motorola MVME162FX Programmer's Reference Manual

MPU Status Register

This logic is duplicated in the VMEchip2 at location $FFF40048, bits
11, 10, 9, and 7. The duplication is to enable ÒNo VMEbus InterfaceÓ
operation. Note that the MPU Status Register in the MC2 chip is
functional independent of the ÒNo VMEbus InterfaceÓ option.
ADR/SIZ
15
BIT
NAME
OPER R
0
RESET
MLTO
MLPE
MLBE
MCLR
$FFF42048 (8 bits)
14 13 12
R R R
0 0 0
When this bit is set, the MPU received a TEA and the
status indicated a local bus time-out. This bit is
cleared by a writing a one to the MCLR bit in this
register. This bit is used with the ÒNo VMEbus
InterfaceÓ option and is duplicated in the VMEchip2
at address $FFF40048 bit 7.
When this bit is set, the MPU received a TEA and the
status indicated a parity error during a DRAM data
transfer. This bit is cleared by writing a one to the
MCLR bit in this register. This bit is used with the
ÒNo VMEbus InterfaceÓ option and is duplicated in
the VMEchip2 at address $FFF40048 bit 9. However,
the MVME162FX does not have parity and this bit is
not implemented.
When this bit is set, the MPU received a TEA and
additional status was not provided. This bit is
cleared by writing a one to the MCLR bit in this
register. This bit is used with the ÒNo VMEbus
InterfaceÓ option and is duplicated in the VMEchip2
at address $FFF40048 bit 10.
Writing a one to this bit clears the MPU status bits 8,
9 and 10 (MLTO, MLPE, and MLBE) in this register.
Programming Model
11 10 9
MCLR MLBE MLPE
C R R
0 PL 0 PL 0 PL
3
8
MLTO
R
0 PL
3-49