Motorola MVME162FX Programmer's Reference Manual page 279

Pacer Clock General Control Register
ADR/SIZ
7
BIT
NAME PLTY
R/W R/W
OPER
RESET 0 R
PS2-0
PS2-PS0
CLR
$FFFBC081 (8 bits)
6 5 4
PLS 0 EN
R R/W
0 R 0 R 0 R
These three bits select the frequency of the pre-scale
logic output The MC68040 bus clock (BCK) is used
as the input to the pre-scale logic. BCK is ether
25 MHz or 32 MHz. BCK frequency can be
determined by examining the Version Register in
the MC2 chip ASIC.
Pre-scaler Output Frequency
PLS = 0
0 BCK/2
1 BCK/4
2 BCK/8
3 BCK/16
4 BCK/32
5 BCK/64
6 BCK/128
7 BCK/256
Setting this bit forces the pacer clockÕs internal
registers (except for the interrupt and general
control registers) to zero. These registers include the
pre-scaler and timer counters. Note that these
registers will remain cleared until the CLR bit is set
to a zero.
Programming Model
3 2 1
CLR PS2 PS1
R/W R/W R/W
0 R 0 R 0 R
PLS = 1
No Output
BCK/2
BCK/4
BCK/8
BCK/16
BCK/32
BCK/64
BCK/128
0
PS0
4
R/W
0 R
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