1.2.9 Host Arm Address Map; 1.2.10 Arm Programming Model; Address Map Of The Mpu Subsystem - Texas Instruments TMS320C6A816 Series Technical Reference Manual

C6-integra dsp+arm processors
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1.2.9 Host ARM Address Map

Region
Boot ROM (128 KB) Secure
ROM Public (48 KB )
Reserved
Reserved
SRAM (64KB) Secure/Public
Reserved
ARM Interrupt Controller (AINTC)
Reserved
Reserved
EMIF0 / EMIF1 CS0
Reserved (EMIF0 / EMIF1 CS1)
Boot Space [1]
L3
Tiler

1.2.10 ARM Programming Model

For detailed descriptions of registers used for MPU configuration, see the Power, Reset, and Clock
Management , and the Interrupt Controller chapters.
1.2.10.1 Clock Control
For clock configuration settings, see the Power, Reset, and Clock Management (PRCM) chapter
1.2.10.2 MPU Power Mode Transitions
The following subsections describe transitions of different power modes for MPU power domain:
Basic power on reset
MPU into standby mode
MPU out of standby mode
MPU power on from a powered off state
1.2.10.2.1 Basic Power-On Reset
The power on reset follows the following sequence of operation and is applicable to initial power-up and
wakeup from device off mode.
1. Reset the INTC (CORE_RST) and the MPU subsystem modules (MPU_RST). The clocks must be
active during the MPU reset and CORE reset.
SPRUGX9 – 15 April 2011
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Preliminary
Table 1-10. Address Map of the MPU Subsystem
Internal Memory (Access not routed to external OCP ports)
Internal Reserved (Audio Back-End port not implemented on device HASS)
Private Peripheral Map (Access not routed to external OCP ports)
128-bit OCP Master Port 0 (to EMIFs via DMM)
64-bit OCP Master Port 1 (to L3)
© 2011, Texas Instruments Incorporated
Address Range
0x4000_0000 – 0x4001_FFFF
0x4002_0000 – 0x4002_BFFF
0x4002_C000 – 0x400F_FFFF
0x4020_0000 – 0x402E_FFFF
0x402F_0000 – 0x402F_FFFF
0x4010_0000 – 0x401F_FFFF
0x4820_0000 – 0x4820_0FFF
0x4820_1000 – 0x4827_FFFF
0x4828_1000 – 0x482F_FFFF
0x8000_0000 – 0xBFFF_FFFF
0xC000_0000 – 0xFFFF_FFFF
0x0000_0000 – 0x00FF_FFFF
0x0000_0000 – 0x5FFF_FFFF
0x6000_0000 – 0x7FFF_FFFF
MPU Subsystem
Size
1MB
1MB
1MB
4KB
508KB
508KB
1GB
1GB
1MB
(1.5GB – 1MB)
256MB
107
Chip Level Resources

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