NEC V850E/RS1 User Manual page 247

(4) Clock control register (CKC)
This is an 8-bit register that controls system clock (f
of MPCCTL register is set to 1). This register can be read or written in 8-bit or 1-bit units.
Be sure to clear bits 2 to 7 of the CKC register to 0. In other case the operation is not guaranteed.
Data can be written to this register only in combination of specific sequences (refer to 3.2.3
Symbol
CKC
R/W
Caution:
Downloaded from Elcodis.com electronic components distributor
"Special registers" on page 70).
Figure 6-13: Clock Control Register (CKC) Format
7 6 5
0 0 0
R R R
CKDIV1 CKDIV0
0 0 Setting prohibited
f
0 1
PLL_MCKSEL_CKDIV
f
1 0
PLL_MCKSEL_CKDIV
f
1 1
PLL_MCKSEL_CKDIV
When operating the CPU and the peripherals by PLL mode, changing the CKC
register is prohibited.
User's Manual U16702EE3V2UD00
Chapter 6 Clock Generator
) when it operates on PLL mode (SELPLL bit
XX
4 3 2
0 0 0 CKDIV1 CKDIV0 FFFFF822H
R R R R/W
System clock (f ) select on PLL mode
XX
= f (PLL internal clock) / 4
PLL
= f (PLL internal clock) / 2
PLL
= f (PLL internal clock)
PLL
1 0 Address After reset
R/W
03H
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