Power On Sequence - NEC V850E/RS1 User Manual

27.9 Power on Sequence

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Chapter 27 Electrical Specification
Figure 27-16: Power on Sequence
V
DD
RESET
PLL
f
CPU
RESET low level
width (t )
RSTL
RESET
f
Low level PLL Factor
X
width
t
8 MHz
RSTL
User's Manual U16702EE3V2UD00
Boot process
OST
f
OST
CPU
X4 32 MHz 1.024 ms
Application code executes
Boot Total
Time Start-up Time
t + 3.053 ms
2.029ms
RSTL
827