NEC V850E/RS1 User Manual page 67

32-/16-bit single-chip microcontroller with can interface
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Program status word (PSW)
A program status word (PSW) is a collection of flags that indicate the program status (instruction
execution result) and the CPU status.
When the contents of this register are changed using the LDSR instruction, the new contents
become valid immediately following completion of the LDSR instruction execution. However, if the
ID flag is set to 1, interrupt request acknowledgement during LDSR instruction execution is prohib-
ited.
Bits 31 to 8 are reserved (fixed to 0) for future function expansion.
PSW
Bit position
31 to 8
Note: During saturated operation, the saturated operation results are determined by the contents of the OV
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Figure 3-6: Program Status Word (PSW) Format (1/2)
31
Flag name
RFU
Reserved field. Fixed to 0.
Indicates that a non-maskable interrupt (NMI) is being serviced. This bit is set to 1
when an NMI request is acknowledged, disabling multiple interrupts.
7
NP
0: NMI is not being serviced.
1: NMI is being serviced.
Indicates that an exception is being processed. This bit is set to 1 when an excep-
tion occurs. Even if this bit is set, interrupt requests are acknowledged.
6
EP
0: Exception is not being processed.
1: Exception is being processed.
Indicates whether a maskable interrupt can be acknowledged.
5
ID
0: Interrupt enabled
1: Interrupt disabled
Indicates that the result of a saturation operation has overflowed and is saturated.
Because this is a cumulative flag, it is set to 1 when the result of a saturation opera-
tion instruction is saturated, and is not cleared to 0 even if the subsequent operation
Note
4
result is not saturated. Use the LDSR instruction to clear this bit. This flag is neither
SAT
set to 1 nor cleared to 0 by execution of an arithmetic operation instruction.
0: Not saturated
1: Saturated
Indicates whether a carry or a borrow occurs as a result of an operation.
3
CY
0: Carry or borrow does not occur.
1: Carry or borrow occurs.
Indicates whether an overflow occurs during operation.
Note
2
0: Overflow does not occur.
OV
1: Overflow occurs.
Indicates whether the result of an operation is negative.
Note
1
0: The result is positive or 0.
S
1: The result is negative.
Indicates whether the result of an operation is 0.
0
Z
0: The result is not 0.
1: The result is 0.
flag and S flag. The SAT flag is set to 1 only when the OV flag is set to 1 during saturated operation. This
is explained on the following table.
User's Manual U16702EE3V2UD00
Chapter 3 CPU Function
RFU
Meaning
8 7
6
5
4
3
2
1
0
After reset
NP
EP
ID
SAT
CY
OV
S Z
00000021H
67

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