NEC V850E/RS1 User Manual page 66

(2) NMI status saving registers (FEPC and FEPSW)
FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs.
If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the
program status word (PSW) are saved to FEPSW.
The address of the instruction next to the one of the instruction under execution, except some
instructions, is saved to FEPC when an NMI occurs.
The current contents of the PSW are saved to FEPSW.
Because only one set of NMI status saving registers is available, the contents of these registers
must be saved by program when multiple interrupts are enabled.
Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved for future function expansion (these
bits are always fixed to 0).
FEPC
FEPSW
(3) Interrupt source register (ECR)
The interrupt source register (ECR) holds the source of an exception or interrupt if an exception or
interrupt occurs. This register holds the exception code of each interrupt source. Because this reg-
ister is a read-only register, data cannot be written to this register using the LDSR instruction.
ECR
Bit position
31 to 16
15 to 0
The list of exception codes is tabulated in Table 17-1, "Interrupt/Exception Source List," on
page 685.
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Chapter 3 CPU Function
Figure 3-4: NMI Status Saving Registers (FEPC and FEPSW) Format
31 26 25
0 0 0 0 0 0
31
0 0 0 0 0 0 0 0 0 0 0 0
Figure 3-5: Interrupt Source Register (ECR) Format
31
FECC
Bit name
FECC Exception code of non-maskable interrupt (NMI)
EICC Exception code of exception or maskable interrupt
User's Manual U16702EE3V2UD00
(PC contents)
8
0 0 0 0 0 0 0 0 0 0 0 0
16 15
EICC
Meaning
0
After reset
0xxxxxxxH
(x: Undefined)
0
After reset
(PSW contents)
000000xxH
(x: Undefined)
0
After reset
00000000H