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• CANn module mask 4 register (CnMASK4L, CnMASK4H)
CnMASK4L CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9
CnMASK4H
CMID28 to CMID0
Remark:
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Chapter 16 FCAN Controller
Figure 16-27: CAN Module Mask Control Register (CnMASKaL, CnMASKaH)
(a = 1, 2, 3, or 4) Format (2/2)
15
14
13
7
6
5
CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1
15
14
13
0
0
0
CMID28 CMID27 CMID26 CMID25 CMID24
7
6
5
CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16
The ID bits of the message buffer set by the CMID28 to CMID0 bits are compared
0
with the ID bits of the received message frame.
The ID bits of the message buffer set by the CMID28 to CMID0 bits are not compared
1
with the ID bits of the received message frame (they are masked).
Masking is always defined by an ID length of 29 bits. If a mask is assigned to a message
with a standard ID, CMID17 to CMID0 are ignored. Therefore, only CMID28 to CMID18 of
the received ID are masked. The same mask can be used for both the standard and
extended IDs.
User's Manual U16702EE3V2UD00
12
11
10
9
4
3
2
1
12
11
10
9
4
3
2
1
Mask pattern setting of ID bit
8
Address R/W After reset
CMID8
R/W undefined
see Table
0
16-16
CMID0
8
0
595
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